Static Timing Analysis Engineer
Qualification: A Bachelor or Masters of Engineering degree in Electrical/ Electronic Engineering/ VLSI Engineering.
Experience: 05 or more years of hands-on experience in Performance (timing) verification, parasitic extraction and design rule quality checks.
IP Design Engineer
Qualification: Bachelor or Master's degree in Computer Science, Electrical or Computer Engineering or related degree.
Experience: 5+ Years of experience with system Verilog and familiarity with a range of internal and 3rd-party logic design tools.
Product Development Engineer
Qualification: BS
Experience: 4+ years of experience in related fields (Electrical Engineer, Computer Engineering/Science and Allied fields).
Location: Bengaluru
For more details, please visit: jobs.intel.com/en/search-jobs/India/599/2/1269750/22/79/50/2
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| Qualification | GRADUATE |
| Experience | 4 year |
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