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Intel Hiring SOC SD Physical Design Engineer

Intel invites application for the post of SOC SD Physical Design Engineer.
Intel Hiring SOC SD Physical Design Engineer

Job Role: SOC SD Physical Design Engineer

Qualifications: Master's degree in EE with at least 6 - 10 years of experience or a Bachelor's degree in EE with at least 8 years of experience in VLSI physical design.

Additional Qualifications:

  • Knowledge of microelectronic designs, semiconductor device physics, CMOS process and physical layout.
  • Good understanding of complete Physical design flow.
  • Hands-on experience in converging complex blocks from RTL to GDSII (more than 500K instances) with embedded macros and low power implementation.
  • Experience with PCIE or LPDDR phy integration is an add-on.
  • Tape out experience with good understanding of latest process nodes DRC's (10nm, 7m/5nm).
  • Experience in automation for design methodology and flow development.
  • Strong debugging skills is must and should come up with technical solutions independently.
  • Experience in logic synthesis, timing constraint development, floorplan, power plan, CTS, routing and timing closure and DRC and LVS closure
  • Experience in backend verification flows like STA, FEV, IR-drop analysis and low power verification.
  • Good hands-on knowledge on EDA tools like Synopsys FC/DC-ICC2, Primetime, Spyglass, Cadence LEC, Ansys Redhawk and Calibre Drv/ICWEBV2.
  • Good knowledge in scripting languages like Tcl and Shell (csh/tcsh/bash).
  • Hands-on Experience in developing utilities in TCL/TK
  • Familiarity with hardware description language such as Verilog or System Verilog
  • Must be a good team player
  • Efficient in working with cross functional/ geo teams with strong communication and leadership skills

Locations: Bengaluru, Hyderabad

For more details, please visit: jobs.intel.com/en/job/bengaluru/soc-sd-physical-design-engineer/41147/60307790768

Also Check: “Success secret” to be an Effective Team Member


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Published date : 22 Jan 2024 05:02PM

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