Digital VLSI Testing Online Course

NPTEL is offering online course for undergraduate/ postgraduate students in Digital VLSI Testing

About the course:

• Testing is an integral part of the VLSI design cycle.
• With the advancement in IC technology, designs are becoming more and more complex, making their testing challenging.
• Testing occupies 60-80% time of the design process.
• A well structured method for testing needs to be followed to ensure high yield and proper detection of faulty chips after manufacturing.
• Design for testability (DFT) is a matured domain now, and thus needs to be followed by all the VLSI designers.

Course Layout:

• Week 1: Introduction: Importance, Challenges, Levels of abstraction, Fault Models, Advanced issues
• Week 2: Design for Testability: Introduction, Testability Analysis, DFT Basics, Scan cell design, Scan Architecture
• Week 3: Design for Testability: Scan design rules, Scan design flow . Fault Simulation: Introduction, Simulation models
• Week 4: Fault Simulation: Logic simulation, Fault simulation
• Week 5: Test Generation: Introduction, Exhaustive testing, Boolean difference, Basic ATPG algorithms
• Week 6: Test Generation: ATPG for non stuck-at faults, Other issues in test generation Built-In-Self-Test: Introduction, BIST design rules
• Week 7: Built-In-Self-Test: Test pattern generation, Output response analysis, Logic BIST architectures
• Week 8: Test Compression: Introduction, Stimulus compression
• Week 9: Test Compression: Stimulus compression, Response compression
• Week 10: Memory Testing: Introduction, RAM fault models, RAM test generation
• Week 11: Memory Testing: Memory BIST Power and Thermal Aware Test: Importance, Power models, Low power ATPG
• Week 12: Power and Thermal Aware Test: Low power BIST, Thermal aware techniques

Duration: 12 weeks

Enrollment Ends: September 21, 2020

For more details, please visit: https://onlinecourses.nptel.ac.in/noc20_ee76/preview